Semiconductor component having test pads and method and apparatus for testing same

ABSTRACT

A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

FIELD OF THE INVENTION

One or more aspects of the present invention relate generally to testingand manufacture of semiconductor devices and, more particularly, to asemiconductor component having test pads and a method and apparatus fortesting the same.

BACKGROUND OF THE INVENTION

Semiconductor dice are typically produced by creating several identicaldevices on a semiconductor substrate, using known techniques ofphotolithography, deposition, and the like. One type of semiconductordie includes bond pads distributed across the entire surface of the diefor supporting bumped contacts. The bond pads are in electricalcommunication with metal layers disposed on the die and withtransistors, resistors, and other electronic circuits integrated withinthe die. After fabrication, the substrate may be “bumped” by formingbumped contacts on each of the bond pads. The bumped contacts aretypically formed of solderable material, such as lead-tin alloy. Bumpeddies are often used for flip chip bonding, where the die is mounted facedown on a supporting substrate, such as a circuit board or lead-frame,by welding or soldering. The mounted die may then be encapsulated or“packaged” to form an integrated circuit.

In practice, certain physical defects in the substrate, as well ascertain defects in the processing of the substrate, inevitably lead tosome of the dice being “good” (i.e., fully-functional) and some of thedice being “bad” (i.e., not-fully-functional). Thus, the dice aretypically tested before being mounted on the supporting substrate. Onetype of conventional testing process involves using a testing device tomake a plurality of discrete pressure connections to the bond pads onthe substrate and provide signals (e.g., power and data signals) to thedice. However, such physical contact may damage the bond pads, which mayruin an entire die or even the entire substrate.

Another type of conventional testing process involves testing the die orsubstrate subsequent to being bumped by making discrete pressureconnections to the bumped contacts. However, such physical contact maydamage the bumped contacts, which may also ruin the bumpeddie/substrate. Specifically, the bumped contacts can become deformedduring testing such that they are unusable to attach the die to thesupporting substrate. Moreover, testing bumped substrate or die resultsin additional expense and undue delay in the manufacturing process ifthe substrate was bad after fabrication.

Accordingly, there exists a need in the art for semiconductor componentscapable of being more easily tested without causing damage thereto, aswell as for improved test procedures for such semiconductor devices.

SUMMARY OF THE INVENTION

One aspect of the invention relates to testing a semiconductorcomponent. An un-bumped substrate is obtained having a pattern of bondpads configured to support bumped contacts and a plurality of test pads.Each of the plurality of test pads is in electrical communication with arespective one of the bond pads. The substrate is tested using theplurality of test pads. Notably, a testing device may contact the testpads without contacting the bond pads, avoiding damage thereto.

Another aspect of the invention relates to fabricating a semiconductorcomponent. A substrate is fabricated having a pattern of bond padsconfigured to support bumped contacts and a plurality of test pads. Eachof the plurality of test pads is in electrical communication with arespective one of the bond pads. The substrate is tested using theplurality of test pads. An insulating layer is formed over the pluralityof test pads. The substrate may be bumped to define bumped contacts forthe bond pads. The substrate may include at least one semiconductor dieformed thereon. The at least one semiconductor die may be mounted to arespective at least one supporting substrate, such as a circuit board orlead-frame. The insulating layer prevents the test pads from interferingwith the bumping and mounting processes.

Another aspect of the invention relates to a semiconductor component. Asubstrate is configured to have at least one conductor layer disposedthereon. The at least one conductor layer includes first portions thatdefine a pattern of bump pads configured to support bumped contacts, andsecond portions that define a plurality of test pads. Each of theplurality of test pads is in electrical communication with a respectiveone of the bond pads. A passivation layer is disposed on the at leastone conductor layer. The passivation layer includes first openingsaligned with the first portions and second openings aligned with thesecond portions. An insulating layer is disposed within the secondopenings.

Another aspect of the invention relates to a semiconductor component. Asubstrate is configured to have at least one conductor layer disposedthereon. The at least one conductor layer includes first portions thatdefine a pattern of bond pads configured to support bumped contacts, andsecond portions that define a plurality of test pads. Each of theplurality of test pads is in electrical communication with a respectiveone of the bond pads. A passivation layer is disposed on the at leastone conductor layer. The passivation layer includes openings alignedwith pairs of the first portions and the second portions. An insulatinglayer is disposed over the second portions.

BRIEF DESCRIPTION OF THE DRAWINGS

Accompanying drawing(s) show exemplary embodiment(s) in accordance withone or more aspects of the invention; however, the accompanyingdrawing(s) should not be taken to limit the invention to theembodiment(s) shown, but are for explanation and understanding only.

FIG. 1 is a plan view depicting an exemplary embodiment of a substrateconfigured in accordance with one or more aspects of the invention;

FIG. 2 is a plan view depicting an exemplary embodiment of asemiconductor component configured in accordance with one or moreaspects of the invention;

FIG. 3 is a cross-sectional view depicting a portion of thesemiconductor component of FIG. 2 taken along the line 3-3;

FIG. 4 is a plan view depicting another exemplary embodiment of asemiconductor component configured in accordance with one or moreaspects of the invention;

FIG. 5 is a cross-sectional view depicting a portion of thesemiconductor component of FIG. 4 taken along the line 5-5;

FIG. 6 is a flow diagram depicting an exemplary embodiment of a processfor fabricating an integrated circuit including a semiconductorcomponent testing process in accordance with one or more aspects of theinvention;

FIGS. 7-8 are sequential cross-sectional views of the semiconductor dieof FIGS. 2 and 3 corresponding to various stages of the process of FIG.6;

FIGS. 9-10 are sequential cross-sectional views of the semiconductor dieof FIGS. 4 and 5 corresponding to various stages of the process of FIG.6; and

FIG. 11 is a block diagram depicting an exemplary embodiment of a systemfor fabricating an integrated circuit including a semiconductor testingunit configured in accordance with one or more aspects of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an exemplary embodiment of a semiconductorcomponent 11 in accordance with one or more aspects of the invention.The semiconductor component 11 comprises a substrate 10 having aplurality of semiconductor circuits formed therein (“semiconductor dice12”) (e.g., twenty are shown). For example, the semiconductor substrate10 may be a wafer or panel having a multiplicity of semiconductor dice12. Although the substrate 10 is illustrated as being generally circularin shape with a major flat edge, the substrate 10 may have a differentshape as is conventionally known in the art. In addition, although thesemiconductor component 11 is illustrated as being a substrate 10 havinga plurality of semiconductor dice 12, it is to be understood that thesubstrate 10 may include only a single semiconductor die 12. Thus, theterm “semiconductor component” is meant to encompass a substrate havingmultiple semiconductor dice, as well as a substrate having a singlesemiconductor die.

FIG. 2 is a plan view depicting an exemplary embodiment of thesemiconductor die 12 of FIG. 1 configured in accordance with one or moreaspects of the invention. FIG. 3 is a cross-sectional view of thesemiconductor die 12 of FIG. 2 taken along the line 3-3 of FIG. 2. Withsimultaneous reference to FIGS. 2 and 3, the semiconductor die 12comprises a semiconductor portion 32 (e.g., silicon) having a desiredelectrical configuration. For example, the semiconductor die 12 mayinclude a processor (e.g., a microprocessor or digital signalprocessor), memory (e.g., dynamic random access memory (DRAM) or staticRAM (SRAM)), programmable logic (e.g., a field programmable gate array(FPGA) or a complex programmable logic device (CPLD)), amask-programmable logic device (e.g., application specific integratedcircuit (ASIC) or application specific standard product (ASSP)), orlike-type integrated circuit devices known in the art. While thesemiconductor die 12 is shown as being generally rectangular in shape,those skilled in the art will appreciate that other shapes may beutilized.

The semiconductor die 12 includes a pattern of die contacts (“bond pads22”) and a pattern of test contacts (“test pads 26”) embedded within adie passivation layer 38. Each of the test pads 26 is in electricalcommunication with one of the bond pads 22 to define test/bond pad pairs24. For purposes of clarity by example, a particular one of thetest/bond pad pairs 24 is denoted as test/bond pad pair 24′, thecross-section of which is illustratively depicted in FIG. 3. Thetest/bond pad pair 24′ includes a particular one of the bond pads 22 anda particular one of the test pads 26, respectively denoted as bond pad22′ and test pad 26′.

The die passivation layer 38 comprises an electrically insulatingmaterial, such as an oxide (e.g., silicon dioxide (SiO₂)), a glass(e.g., borophosphosilicate glass (BPSG)), a polymer (e.g., polyimide),or like-type insulation material known in the art. The bond pads 22, thetest pads 26, and the die passivation layer 38 are disposed on acircuit-side 20 of the semiconductor die 12, with the bond pads 22 andthe test pads 26 disposed below the level of the die passivation layer38.

The bond pads 22 and the test pads 26 may be generally square asillustrated in FIG. 2, or may have other shapes known in the art (e.g.,other polygonal or elliptical shapes). Moreover, the bond pads 22 andthe test pads 26 may have the same shape as shown (e.g., each of thebond pad 22′ and the test pad 26′ having a generally square shape), ormay have different shapes (e.g., the bond pad 22′ having one shape, andthe test pad 26′ having a different shape). The bond pads 22 may be ofany size and the pattern of the bond pads 22 may have any pitch. Forexample, the bond pads 22 may have a size between, but not limited to,25 μm and 200 μm on a side. The pattern of the bond pads 22 may have apitch between, but not limited to, 90 μm and 130 μm. The bond pads 22may be configured in a staggered grid pattern as shown in FIG. 2, or maybe arranged in other configurations known in the art (e.g., a perimeterpattern).

The test pads 26 may be smaller in size than the bond pads 22 as shown.Alternatively, the test pads 26 may be the same size or larger in sizethan the bond pads 22. For example, the test pads 26 may have a sizebetween, but not limited to, 25 μm and 100 μm on a side. The test pads26 are interspersed among the bond pads 22. Notably, the test pads 26may be disposed within interstitial regions defined by the bond pads 22,within a perimeter region defined by the bond pads 22 and thesemiconductor die 12, or both. Illustratively, the test pad 26′ may bedisposed at any point around the perimeter of the bond pad 22′ within aparticular distance limited by the pitch of the pattern of the bond pads22. For example, the test pad 26′ may be separated from the bond pad 22′by a distance of, but not limited to, at least 2 μm.

The semiconductor die 12 includes a top conductor layer 36 in electricalcommunication with the various semiconductor devices (semiconductorcircuits) within the semiconductor portion 32. The semiconductor die 12may also include an internal conductor portion 34 comprising one or moreinternal conductor layers between the substrate portion 32 and the topconductor layer 36. All of the conductor layers may be separated byrespective insulating layers, and may be connected to each other usingvias (not shown for simplicity). The internal conductor portion 34 maybe in electrical communication with the top conductor layer 36 and thesemiconductor devices/circuits within the semiconductor portion 32.

The conductors of the top conductor layer 36 and the internal conductorportion 34 may be formed using a conventional semiconductor fabricationprocess, which may include a deposition process. Suitable materials forthe conductors of the top conductor layer 36 and the internal conductorportion 34 include, for example, aluminum, chromium, titanium, nickel,iridium, copper, gold, tungsten, silver, platinum, tantalum, molybdenum,as well as alloys of such metals.

The passivation layer 38 is formed over the top conductor layer 36. Eachof the bond pads 22 is located in an opening 42 of the passivation layer38 and comprises a portion 44 of the top conductor layer 36. Each of thetest pads 26 is located in an opening 40 of the passivation layer 38 andcomprises a portion 46 of the top conductor layer 36. The top conductorlayer 36 electrically couples the bond pads 22 with respective ones ofthe test pads 26 (e.g., the top conductor layer 36 electrically couplesthe bond pad 22′ with the test pad 26′). In the present embodiment, eachof the bond pads 22 is laterally separated from a respective one of thetest pads 26 by a portion 48 of the passivation layer 38. The test pads26 may be considered as “extended test pads” with respect to the bumppads 22.

The bond pads 22 are adapted to support bumped contacts (e.g., solderballs) for providing external electrical connections for thesemiconductor die 12. Once the bumped contacts are in place, thesemiconductor die 12 may be “flip chip” mounted (i.e., circuit-sidedown) to mating electrodes on a supporting substrate, such as a circuitboard or lead-frame. After mounting, the semiconductor die 12 may bepackaged or encapsulated to form an integrated circuit (e.g., ball gridarray (BGA) package, chip scale package (CSP), and like-type packagesknown in the art). As described below, the test pads 26 may be used totest the semiconductor die 12 before the semiconductor die 12 is bumpedand without contacting the bond pads 22.

FIG. 4 is a plan view depicting another exemplary embodiment of thesemiconductor die 12 of FIG. 1 configured in accordance with one or moreaspects of the invention. FIG. 5 is a cross-sectional view of thesemiconductor die 12 of FIG. 4 taken along the line 5-5. Elements inFIGS. 4 and 5 that are the same or similar to those shown in FIGS. 2 and3 are designated with identical reference numerals and are described indetail above.

With simultaneous reference to FIGS. 4 and 5, in the present embodiment,the semiconductor die 12 includes a pattern of test/bond pad pairs 24Aembedded within the die passivation layer 38. Each of the test/bond padpairs 24A comprises a die contact portion (“bond pad 22A”) in electricalcommunication with a test contact portion (“test pad 26A”). FIG. 5 showsa cross-section of one of the test/bond pad pairs 24A.

In the present embodiment, each of the test/bond pad pairs 24A islocated in an opening 52 of the passivation layer 38 and comprises asection 50 of the top conductor layer 36. A first portion of the section50 defines the bond pad 22A, and a second portion of the section 50defines the test pad 26A. That is, the bond pad 22A and the test pad 26Acomprise separate regions of the section 50 of the top conductor layer36. The top conductor layer 36 electrically couples the bond pad 22Awith the test pad 26A. The test pad 26A may be considered as an“extended test pad” with respect to the bump pad 22A.

The test/bond pad pairs 24A may be arranged in any pattern having anypitch (e.g., a staggered grid pattern having a pitch between, but notlimited to, 90 μm and 130 μm). The shapes and sizes of the bond pad 22Aand the test pad 26A may be selected substantially as described abovewith respect to FIGS. 2 and 3. Notably, the test pad 26A may be smallerin size that the bond pad 22A as shown. Alternatively, the test pad 26Amay be the same size or larger in size than the bond pad 22A. Asdescribed below, for each of the test/bond pad pair 24A, the test pad26A may be used to test the semiconductor die 12 before thesemiconductor die 12 is bumped and without contacting the bond pad 22A.

FIG. 6 is a flow diagram depicting an exemplary embodiment of a process600 for fabricating an integrated circuit. The process 600 includes aprocess 601 for testing a semiconductor component in accordance with oneor more aspects of the invention. The process 600 begins at step 602. Atstep 604, a semiconductor substrate is fabricated by forming a pluralityof semiconductor dice thereon. The semiconductor substrate may include aplurality of semiconductor components or dice. While the process 600 isdescribed with respect to a semiconductor component comprising asubstrate with a plurality of semiconductor dice, it is to be understoodthat the semiconductor component may include a substrate having a singlesemiconductor die.

In either case, each semiconductor die is fabricated with a desiredelectrical configuration (e.g., processor, memory, etc.) and includes apattern of bond pads in electrical communication with test pads (alsoreferred to herein as “extended test pads”). The bond pads are adaptedto support bumped contacts (e.g., solder balls). The integrated circuitfabrication process is well-known in the art. As such, the details ofsuch processes are not discussed herein. The semiconductor substrate 10fabricated at step 604 is then tested in accordance with the testprocess 601.

The test process 601 comprises steps 606 through 612. At step 606, thesemiconductor substrate is tested using the extended test pads. Notably,a “tester” or “prober” may be employed to make discrete pressureconnections with the extended test pads and to provide signals (e.g.,data and/or power signals) to excite or “exercise” the semiconductordevices/circuits on the substrate, and to receive results from thedevices/circuits. In this manner, the die or dice of the substrate maybe tested or “burned-in” before further processing (e.g., bumping,packaging, etc.). In addition, the testing device does not make contactwith the actual bump pads, which avoids potential damage to the bumppads. Moreover, the semiconductor substrate may be tested before thesubstrate is bumped (i.e., an “un-bumped” substrate), which avoidspotential damage to the bumped contacts.

At step 608, a determination is made as to whether the substrate shouldbe further processed. If not, the process 601 proceeds to step 610,where the substrate is discarded. For example, the substrate may bediscarded if a single semiconductor die has failed the test at step 606.Alternatively, the substrate may be discarded if a plurality ofsemiconductor dice has failed the test at step 606. The number ofacceptable failures may be determined with respect to the cost offabrication versus the cost of the further processing (e.g., cost ofbumping/packaging). In this manner, if the semiconductor substrate failsthe test at step 606, processing costs are mitigated and processing timeis saved.

If at step 608 the substrate is to be further processed, the process 601proceeds to optional step 612. At step 612, the extended test pads ofthe substrate 10 are covered with an insulating layer such as, but notlimited to, polyimide or bisbenzocyclobutene (BCB). Alternatively,rather than forming or depositing an insulating layer at step 612, theinsulating layer may be formed as part of a conventional bumping process(e.g., step 614 described below).

If the substrate is not discarded during the testing process 601, thefabrication process 600 proceeds to step 614. At step 614, thesemiconductor substrate is bumped. That is, bumped contacts (e.g.,solder balls) are formed on the substrate in electrical communicationwith the bump pads using a conventional bumping process. As part of theconventional bumping process, an insulating layer may be formed on theentire substrate with the exception of the bump pads before the bumpedcontacts are formed. In this manner, the extended test pads may becovered with the insulating layer. Alternatively, an insulating layermay be pre-formed at step 612, as described above.

At step 616, each semiconductor die on the substrate is flip chipmounted to mating electrodes on a supporting substrate using aconventional mounting process. For example, each semiconductor die maybe flip chip mounted to a circuit board or lead-frame. The semiconductordie may then be packaged to form an integrated circuit (e.g., BGA, CSP,or the like). If the substrate includes multiple dice, the dice aresingulated (i.e., diced) before mounting. The process 600 ends at step618.

FIGS. 7-8 are sequential cross-sectional views of the semiconductor die12 of FIGS. 2 and 3 corresponding to various stages of the process 600of FIG. 6. In particular, FIG. 3 depicts a cross-section of thetest/bond pad pair 24′ after fabrication at step 604. FIG. 7 depicts across-section of the test/bond pad pair 24′ during the testing at step606. Notably, a probe element 702 is in contact with the portion 46 ofthe top metal layer 36 defining the test pad 26′. The probe element 702does not contact the portion 44 of the top metal layer 36 defining thebond pad 22′. Thus, damage to the bond pad 22′ is avoided during thetesting at step 606.

FIG. 8 depicts a cross-section of the test/bond pad pair 24′ afterbumping at step 614. Notably, an insulating layer 802 covers thepassivation layer 38 and the test pad 26′. The insulating layer 802 maybe formed during the step 612, or may be formed during the bumpingprocess in step 614. The insulating layer 802 is not formed over thebond pad 22′. Rather, a bumped contact 804 is formed in electricalcommunication with the bump pad 22′.

FIGS. 9-10 are sequential cross-sectional views of the semiconductor die12 of FIGS. 4 and 5 corresponding to various stages of the process 600of FIG. 6. In particular, FIG. 5 depicts a cross-section of thetest/bond pad pair 24A after fabrication at step 604. FIG. 9 depicts across-section of the test/bond pad pair 24A during the testing at step606. Notably, a probe element 902 is in contact with the portion of theconductor section 50 that defines the test pad 26A. The probe element902 does not contact the portion of the conductor section 50 thatdefines the bond pad 22A. Thus, damage to the bond pad 22A is avoidedduring the testing at step 606.

FIG. 10 depicts a cross-section of the test/bond pad pair 24A afterbumping at step 614. Notably, an insulating layer 1002 covers thepassivation layer 38 and the portion of the conductor section 50 thatdefines the test pad 26A. The insulating layer 1002 may be formed duringthe step 612, or may be formed during the bumping process in step 614.The insulating layer 1002 is not formed over the portion of theconductor section 50 that defines the bond pad 22A. Rather, a bumpedcontact 1004 is formed in electrical communication with the bump pad22A.

FIG. 11 is a block diagram depicting an exemplary embodiment of a system1100 for fabricating an integrated circuit configured in accordance withone or more aspects of the invention. The system 1100 may be adapted toperform the process 600 of FIG. 6. Notably, the system 1100illustratively comprises a fabrication unit 1102, a testing unit 1104, abumping unit 1106, and a mounting unit 1108. The fabrication unit 1102is adapted to fabricate substrates having a desired electricalconfiguration and a pattern of bond pads in electrical communicationwith test pads.

Substrates fabricated by the fabrication unit 1102 are fed to thetesting unit 1104. The testing unit 1104 includes a tester or prober,such as probe card and associated control circuitry, for testing thesubstrates using the test pads. Substrates that pass the test(s)performed by the testing unit 1104 are fed to the bumping unit 1106,where the substrates are bumped. Bumped substrates from the bumping unit1106 are fed to the mounting unit 1108. In the mounting unit 1108, eachsemiconductor die on the substrate may be mounted to a supportingsubstrate (e.g., circuit board or lead-frame) and may be packaged toform an integrated circuit.

While the foregoing describes exemplary embodiment(s) in accordance withone or more aspects of the present invention, other and furtherembodiment(s) in accordance with the one or more aspects of the presentinvention may be devised without departing from the scope thereof, whichis determined by the claim(s) that follow and equivalents thereof.Claim(s) listing steps do not imply any order of the steps. Trademarksare the property of their respective owners.

1. A method of testing a semiconductor component, comprising: obtainingan un-bumped substrate having a pattern of bond pads configured tosupport bumped contacts and a plurality of test pads, each of saidplurality of test pads being in electrical communication with arespective one of said bond pads; and testing said substrate using saidplurality of test pads.
 2. The method of claim 1, wherein said testingstep comprises: contacting said plurality of test pads with a testingdevice without contacting said bond pads.
 3. The method of claim 1,wherein said substrate includes a conductive layer and a passivationlayer disposed on said conductive layer, said conductive layer includingfirst portions defining said bond pads and second portions defining saidplurality of test pads, said passivation layer including first openingsaligned with said first portions and second openings aligned with saidsecond portions.
 4. The method of claim 3, wherein said testing stepcomprises: contacting only said second portions with a testing device.5. The method of claim 1, wherein said substrate includes a conductivelayer and a passivation layer disposed on said conductive layer, saidconductive layer including first portions defining said bond pads andsecond portions defining said plurality of test pads, said passivationlayer having openings aligned with pairs of said first portions and saidsecond portions.
 6. The method of claim 5, wherein said testing stepcomprises: contacting only said second portions with a testing device.